Warp is a data orchestration and synchronization layer for distributed Go backends.
Efficient caching for non-volatile memory-backed search indices. A thesis submitted for undergraduate honours for the degree Software Engineering.
A direct-mapped L1 cache supporting byte-, halfword-, and word-level accesses. Implements read-allocate on read miss and write-around on write miss, with proper hit/miss handling. Both design and verification focus on correctness across various access patterns.
This repository contains files related to Computer Architecture Lab (Autumn 2022).
Deep dive into Cache and related concepts with this interactive playground.
A from-scratch C++ implementation of a cache-aware CPU scheduler featuring score-based task selection, starvation prevention, and L1/L2/L3 cache simulation.
Inspired implementation of Paper: "AgentOS: From Token-Level Context to Emergent System-Level Intelligence". https://arxiv.org/html/2602.20934v1
A Verilog implementation of a two-level cache hierarchy with direct-mapped L1, 2-way set-associative L2, FSM controller, latency modeling, and simulation testbench.
Verilog implementation of L1 cache (direct-mapped, 4-way, fully-associative) with simulation outputs
Personal repository for COL216 assignments - pardon mistakes!
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